1. Field of the Invention
This invention relates to flash memory arrays in general, and more particularly to a novel byte-programmable and byte-erasable flash memory array having on-chip counter means and secondary storage means for the control of word line and bit line disturbances during program and erase operations.
2. Description of the Prior Art
Semiconductor memories are considered one of the crucial microelectronics components for mainframe computers, personal computers, telecommunication equipment, automotive and consumer electronics, commercial and military avionics systems, and so on. Semiconductor memory devices include both volatile random access memories (RAMs) and nonvolatile memory devices (NVMs). The data stored in an NVM are not lost when the power supply is removed. Depending on the design and the fabrication technology, nonvolatile memory data storage mode may be either permanent or re-programmable. Various categories of NVMs have been developed in the art, including mask read-only memory (mask ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically alterable read-only memory (EAROM), electrically erasable programmable read-only memory (EEPROM or E.sup.2 PROM), nonvolatile static random access memory (NVRAM), and the flash memory.
One of the most important erasable-programmable NVMs is the flash memory device, in which the contents of all the memory cells in an array or in a section or block of an array can be erased simultaneously through the use of an electrical erase signal. A flash memory cell can be based on either EPROM or E.sup.2 PROM technology, the latter typically requiring a select transistor and a floating gate transistor per memory cell. The choice between the flash E.sup.2 PROM memory and the flash EPROM memory thus depends on the tradeoffs between the higher density of the EPROM technology and the in-circuit programming flexibility of the E.sup.2 PROM technology. Most conventional flash memories have been based on EPROM in view of its compactness, speed and relatively low cost.
The structure of a flash memory cell is essentially the same as that of an EPROM or E.sup.2 PROM memory cell. Thus, a floating gate transistor having a floating gate, typically located between a control gate and a substrate, is used to store electrical charges that represent a data bit.
FIG. 1 is a cross-sectional view of a conventional stacked-gate flash EPROM memory cell transistor 10 as fabricated in a flash EPROM array. Typically, the substrate 12 is a monocrystalline silicon wafer having a first conductivity type dopant, e.g., the p-type. The substrate 12 has a source region 14 and a drain region 16, both doped with a second conductivity type dopant, e.g., the n-type. A channel zone 18 is defined by the near-surface area of the substrate 12 between the source 14 and the drain 16.
The flash memory cell shown in FIG. 1 has two gates: the floating gate 20 and the control gate 22. The floating gate 20 and the control gate 22 are usually made of the same material, i.e., polysilicon. Layers of dielectric materials 24 are deposited between the substrate 12 and the floating gate 20 (e.g., silicon dioxide) and between the floating gate 20 and the control gate 22 (e.g., an oxide-nitride-oxide interpoly dielectric). The dielectric (oxide) layer between the substrate 12 and the floating gate 20 is the gate oxide layer 26. As shown in FIG. 1, the floating gate 20 in the flash memory cell 10 typically overlaps with the edges of the source region 14 and the drain region 16.
When the floating gate 20 of a flash memory cell 10 carries no charge, the floating gate 20 has no influence on the electric field generated by the active control gate 22 in the channel zone 18. However, once the floating gate 20 is charged with electrons, the charge on the floating gate 20 will generate in the channel zone 18 an electrical field opposite to the field generated by the active control gate 22, thus raising the threshold voltage (V.sub.t) of the flash memory cell, i.e., the control-gate-to-source potential difference required to turn on the cell. Following the convention used in the EPROM technology, the memory cell charging operation is typically referred to as the "program" operation, while the discharging operation is typically referred to as the "erase" operation.
Typically, to program the flash EPROM cell transistor 10, a control gate voltage of +9 to +12 V is applied to the control gate 22, a typical drain voltage of +5 to +6 V is applied to the drain 16, and the source 14 is grounded. These conditions create an electric field that causes electrons to flow from the source region 14 to the drain region 16. In addition, an electric field is created by the large positive voltage at the control gate 22. Some of the electrons moving from the source 14 to the drain 16 will have sufficient energy (i.e., "hot electrons") to pass through the gate oxide 26 and collect on the floating gate 20 to represent a data bit. This process is the so-called channel hot carrier injection ("HCI") programming. The amount of charge transferred to the floating gate 20 is very time-dependent. A typical program operation will require the above voltages be present for a relatively long duration, e.g., 10 .mu.sec. As a comparison, a typical read operation takes less than 100 nsec.
In a typical "read" operation of a flash memory cell, the drain region 16 is connected to a small positive voltage of +1 to +2 V while the source region 14 is grounded. A positive voltage, e.g., +5 V, is applied to the control gate 22. As described above, the electrical charges present on the floating gate 20 will alter the threshold voltage of the cell. A cell which is erased or not programmed has a relatively low threshold voltage of about +2 V (i.e., low V.sub.t state), while a programmed cell has a relatively high threshold voltage of +5 to +6 V (i.e., high V.sub.t state). Thus, if a memory cell 10 has been programmed, the gate-to-source voltage of +5 V will be close to the programmed threshold voltage, so that little current will flow. This absence of cell current indicates that the cell is in a programmed state. By common convention, a memory cell in the programmed state has a logic state of "0". If, on the other hand, the memory cell 10 is in an erased or unprogrammed state, the control-gate-to-source voltage of +5 V will exceed the threshold voltage of +2 V and cause the cell to conduct a current. The presence of a cell current indicates that the cell is in an erased state. Again by common convention, a memory cell in the erased state has a logic state of "1". During a read operation, the cell current is converted to a voltage, which is then compared with a reference voltage by a sense amplifier (not shown in FIG. 1). The output of the sense amplifier will indicate whether the cell is programmed (a logic "0") or erased (a logic "1").
A flash memory cell 10 can be erased in a number of ways. For example, in the so-called negative-gate source erase, a control gate voltage of approximately -10 V and a source voltage of approximately +5 V are respectively applied, while the drain 16 is allowed to float. These erase voltages enable electrons to be driven from the floating gate 20 to the source 14, typically via the Fowler-Nordheim tunneling mechanism. Source erase allows a "page-erase" that can erase typically 512 or 128 bytes at a time. Another example of the source erase operation involves applying a large positive voltage (e.g., +10 V) to the source region 14, allowing the drain 16 to float, and connecting the control gate 22 to ground. Still another example of the erase operation is the channel erase, in which charges on the floating gate 20 are caused to move to the substrate 10 rather than to the source 14, again through the Fowler-Nordheim tunneling mechanism. To implement effective source erase or negative-gate source erase, a double-diffused implant (DDI) (not shown in FIG. 1) is generally introduced into the source regions 14.
In a conventional flash memory array, each time a memory cell (representing a bit) is re-programmed, it must first be in the erased state having a logic state of "1". This is because cell programming can only change the threshold voltage from low to high, corresponding to a change from a logic "1" to a logic "0". Thus, to program a selected memory cell in a conventional flash memory, the word line (described below) to which the control gate of the cell is connected and the bit line (also described below) to which the drain of the cell is connected must first be selected, and the entire sector or even the whole array containing the selected cell must first be erased before it can be programmed. Consequently, programming and erasing conventional flash memories are often time-consuming tasks that require a specialized command protocols comprising command sequences of read, program, and erase for writing data to selected memory locations.
A flash memory array contains many individual memory cells orthogonally interconnected along word lines ("WL's") and bit lines ("BL's"). A typical flash memory array configuration is the so-called common source NOR-type NVM array. A layout representation of a portion of a common source NOR-type flash memory array 30 is shown in FIG. 2. In the NOR array 30, n+ diffused Vss metal common source lines 32 are placed every 16 to 64 metal bit lines 34 in the array 30 to provide connections 36 to n+ source buses 38. The Vss common source lines 32 and bit lines 34 are parallel to each other. Source buses 38, also essentially parallel to each other, are in addition essentially parallel to the polysilicon word lines 40. Each of the metal bit lines 34 provides connections 42 to the individual drain areas 44. Furthermore, as discussed above, implanted wells are typically used to provide isolated regions in the substrate, e.g., a p-type well or a double (p/n) well (not shown in FIG. 2).
Ideally, a flash memory should last forever. However, whenever an erase is performed on a flash memory cell, the transistor is stressed; if the transistor is then re-programmed, it is stressed once again. In an conventional flash memory erase operation, all the transistors in the page, sector or even entire array are stressed. Repeated stress inevitably reduces the life of the memory array over time. Because the sector/array erase is time-consuming, computers or electronic devices containing a conventional flash memory often encounter undue delays in changing the information in the flash memory and delays in regaining access to the flash memory. Therefore, it is highly desirable to develop a flash memory array that can be erased and programmed in a selected number of bits, e.g., bytes.
A flash memory should ideally maintain a programmed state indefinitely if such is desired. In reality, however, the size of the individual memory cells is constantly being reduced in order to increase the storage capacity of the semiconductor memory. This reduction in cell size has been accompanied by a decrease in the data retention of the cells, owing in a large part to the increased tendency to disturb the programmed state of the cells during various memory operations. The ability of a flash memory to retain data over a long time period is mainly affected by three types of disturbances, including "read disturb," "word line disturb," and "bit line disturb."
Read disturb occurs when a memory cell 10 of FIG. 1 becomes slightly programmed (i.e., its floating gate 20 is slightly charged) by way of the hot electron injection during a read operation. Thus, an electric field is created between the source region 14 and the drain region 16 due to the positive voltage (+1 to +2 V) applied to the drain region 16. This electric field causes a very small percentage of the electrons traveling between the drain and source regions to obtain sufficient energy to be drawn up to the floating gate 20 by the positive voltage of the control gate 22. This is true even though the time required to perform a read operation is much less than that required to perform a conventional program operation. Because the strength of the aforesaid electric field between the drain and the source is inversely proportional to the length of the channel zone 18, the read disturb phenomenon becomes more pronounced as cell geometries become smaller.
When a large positive voltage is applied to the control gate of a memory cell, with that control gate being connected to a word line of the array, word line disturb take places at the unselected cells on the same word line. For example, if one word line has 1024 cells, there are as many as 1016 unselected cells on the same word line during a byte-erase or program operation. These unselected cells on the same word line will experience the high-voltage stress or "WL disturb" during the erase or program operation. Compared to read line disturb, WL disturb is much more pronounced because of the relatively high voltage used in a program or erase operation. Similarly, bit line disturb takes place at the unselected cells on a bit line as one or more of the cells of the same bit line are selected for program or erase. For example, if one bit line has 64 cells and one bit on the same bit line is selected for program or erase, the other 63 unselected cells on the same bit line will experience the high voltage stress or "BL disturb" during the program or erase operation. Generally, the higher the program or erase voltage is and the smaller the memory cells become, the more aggravated is the problem of disturbance to adjacent cells on the same word line or the same bit line. It is thus highly desirable to develop a byte- or bit-programmable flash memory having advanced disturb control features.